The present invention relates to the interface between a semiconductor chip and other elements in a computer system.
At the present time, computers other than very small computers utilize a large number of small chips to perform arithmetic and memory functions. Significant spacing is generally provided between the chips because of the necessity of heat dissipation. Each chip contains various logic and memory circuits, and the circuits on the various chips communicate with one another and with other elements in the system by means of signals. The signals are carried by conductors which interconnect the various elements in the system, and the transmission time for each particular signal is significant relative to the overall computation speed of a computer because of the spacing between the various chips and other elements. Considering the high volume of signals that must be exchanged, the aggregate transmission time for the numerous signals transmitted represents a very substantial limitation on overall system speed.
One technique for at least partially resolving the system speed limitations arising from the use of a large number of small chips is the substitution of a relatively fewer number of large chips for the numerous small chips. When large chips are employed, many of the communications between various logic and memory circuits will be made between circuits on the same chip, and because of the close proximity of the circuit elements the transmission time is virtually nil.
One of the difficulties in the utilization of large chips, however, is the fact that the various circuit elements must communicate with one another, and must have sources of power and ground as well. Typically, contacts are provided about the periphery of a chip, with the various circuit elements exchanging signals, receiving power and providing a ground through these contacts. When the dimensions of the chip are increased, the number of circuit elements which can be accommodated on a given chip rises much more rapidly than the number of contacts which can be accommodated about its periphery. Also, the necessity of providing transverse leads from the circuits to the edge of the chip adds complexity to an already complex device.
Attempts have been made to construct semiconductor chips with a two dimensional array of contacts, to solve the problem of providing transverse leads and sufficient peripheral contacts when the number of circuits is enlarged. To connect such a chip to other elements, the chip is typically located substantially flush with a printed circuit board or other flat surface with multiple connections, and the chip contacts are coupled to the connections with multiple pinpoint solder connections. Unfortunately, there is typically thermal expansion mismatch between the chip and the printed circuit board, both during assembly and in use, resulting in stresses on the connections which can break the connection, or worse, fracture the delicate semiconductor chip circuits. As chip size increases, the effect of thermal expansion mismatch becomes more pronounced, and the problem is magnified.